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 embedded Motorola PowerPC

Freescale PowerProzessoren

Hintergrund:

Nach dem Erfolg mit den Netzwerkprozessoren MPC860/855/850 wurde die Familie 82xx kräftig ausgebaut und bereits schimmert die nächste Generation PowerQuicc III mit MPC8540 und MPC8560, denn für viele Anwendungen ist der 603 core im PowerQuicc II doch etwas schwachbrüstig. Mit e500 ist ein neues Core Konzept entstanden, welches auch in der nächsten Generation PowerPC embedded controller, MPC 5500, MPC 5600, Einzug hält und neuen Anwendungen ein Herz von Motorola ermöglicht.

MPC8540 MPC8560 integrated host processors are Freescale's first devices utilizing the e500 core; the industry's first RapidIO-enabled processors. Balancing processor performance with I/O system throughput, the MPC8540/8560 are powerful for network routers and switches, storage subsystems, network appliances, and print and imaging devices.

The MPC8540/8560 integrate dual IEEE 802.3 10/100/1G Ethernet controllers (support jumbo frames and Layer 2 acceleration), a 10/100 controller, a 64-bit PCI-X controller operating at up to 133 MHz, a DDR memory controller, a 4-channel DMA, a multi-channel interrupt controller, and a DUART serial interface. The MPC8540/8560 also integrates the e500 core, 256 KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), providing cross-sectional bandwidth of up to 22 Gbps peak bandwidth per port together with independent transaction queuing and flow control.

MPC85xx common Features

• Embedded e500 Book E compatible core available from 600 MHz up to 1 GHz
• 32-bit, dual-issue, superscalar, seven-stage pipeline
• 1850 MIPS at 800 MHz (est. Dhrystone 2.1)
• 32 KB L1 data and 32 KB L1 instruction cache with line locking support
• 256 KB on-chip L2 cache with direct mapped capability
• Memory management unit (MMU), 4-channel DMA, Interrupt controller
• SIMD extension with single precision floating point
• Two triple-speed Ethernet controllers 10/100/1000 Mbps Ethernet (IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII interfaces.
• 166 MHz, 64-bit, 2.5V I/O, DDR SDRAM memory controller with full ECC support
• 500 MHz, 8-bit, LVDS I/O, RapidIO controller
• 133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 bus controller
• 166 MHz, 32-bit, 3.3V I/O, local bus with memory controller
• 10/100 Ethernet controller (802.3) for chip debug and maintenance support
• IEEE 1149.1 JTAG test access port, enhanced hardware and software debug support
• 1.2V core power supply with 3.3V and 2.5V I/O
• 783-pin FC-BGA package

Background:

In the mid-90s Freescale's PowerPC product lines have stepped out of the shadow of the old IBM heritage and the 601 inspired little-endian / Map A designs soon will be a thing of the past. PowerQuicc 850/860 have enabled the fast Internet for many of us while PowerQuicc II 8260 with derivates now include the most wanted PCI interface as well as different cache and DMA options. PowerQuiCC III presents the powerful e500 core to keep going places where the 603 core of the 82xx architecture was out of breath, many applications used 8260 as slave(s) to 750/755 or Altivec 7400. Speaking of higher performance, this Altivec 7400 has spawned its derivatives 7410/40 and 7450/7451/7455 which are popular among power-users, not only in Apple's cool G4 machines.

And there's more to come, the PowerQuiCC MPC 8xx series had a facelift and are breaking speed barriers with MPC 857 and MPC 862, automotive customers now have a wide range of MPC 5xx to choose from, including Nexus debugging interface to capture the action when it is happening. Based on the same e500 core, Motorola announced powerful embedded controller MPC 5600 series to take automotive and industrial control applications one step further.

e500 Core

Utilizing an SoC platform which balances MIPS, Watts, packet performance and cost, Motorola has created a flexible platform architecture. The e500 high performance core implements the enhanced PowerPC Book E instruction set architecture and provides unprecedented levels of hardware and software debug support. The e500 will serve as the core for a family of ASSPs for communications, automotive and consumer applications.

RapidIO Interconnect

RapidIO offers significantly greater bandwidth, scalability and reliability than traditional interconnects, yet is compatible with existing PCI and CPU architectures. It has a flexible architecture that can easily adapt to changing industry needs without affecting existing infrastructure. RapidIO is an open standard governed by an industry body, designed specifically for embedded, networking and communications applications.

MPC8560 only Features

• High-performance RISC CPM available at up to 333 MHz
• CPM software compatibility with previous families
• Greater than 1 Gbps aggregate CPM bandwidth
• 32 KB of dual-port RAM, 128 KB of ROM + 32 KB of RAM for protocol microcode storage
• Two UTOPIA Level II master/slave ports with multi-PHY support (one can be 16-bit)
• Three MII interfaces
• Eight TDM interfaces (T1/E1), two TDM ports that can be interfaced with T3/E3
• Four SCCs supporting HDLC and SDLC, HDLC bus, UART, Transparent, BISYNC
• Three FCCs supporting up to 155 Mbps ATM, 10/100 Mbps Ethernet IEEE 802.3X, or 45 Mbps transparent HDLC
• Two MCCs each supporting 128 full-duplex, 64 kbps, HDLC lines for a total of 256 channels
• ATM transmission convergence layer capable, integrated inverse multiplexing for ATM (IMA) functionality

Motorola MPC 505 509 555 556 565 563 561 5600 603 740 70 755 7400 7410 7450 7451 7455 801 821 823 850 855 857 860 862 8240 8245 8260 8261 8264 8265 8540 8560 e500

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